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        <title>JobLance.inFo Verilog / VHDL Job Feeds</title>
        <description><![CDATA[JobLance.inFo - Latest Verilog / VHDL Jobs and Projects]]></description>
        <link>http://joblance.info</link>
        <lastBuildDate>Sat, 26 May 2012 20:13:00</lastBuildDate>
        <generator>JobLance Feed Creator</generator>
        <item>
            <title>Face Recognition using FPGA</title>
            <link>http://joblance.info/1392934/face-recognition-using-fpga</link>
            <description><![CDATA[Face recognition is very important technology in view of security threats world is facing. It is implemented.....]]></description>
            <pubDate>Tue, 22 May 2012 15:00:06</pubDate>
            <guid>http://joblance.info/1392934/face-recognition-using-fpga</guid>
        </item>
        <item>
            <title>Verilog - Digital video Camera   Zoom using DE2-70 board</title>
            <link>http://joblance.info/1368315/verilog-digital-video-camera-zoom-using-de2-70-board</link>
            <description><![CDATA[The project is divided into 2 parts    1st part: Basic requirements     2nd part: Advanced requirements.....]]></description>
            <pubDate>Tue, 08 May 2012 12:00:06</pubDate>
            <guid>http://joblance.info/1368315/verilog-digital-video-camera-zoom-using-de2-70-board</guid>
        </item>
        <item>
            <title>solving some problems</title>
            <link>http://joblance.info/1367076/solving-some-problems</link>
            <description><![CDATA[writing a paper about some books and do some code for c ++ and and do exams for CIV also discussing online.....]]></description>
            <pubDate>Mon, 07 May 2012 21:00:07</pubDate>
            <guid>http://joblance.info/1367076/solving-some-problems</guid>
        </item>
        <item>
            <title>32bit single precision floating point addition unit(verilog)</title>
            <link>http://joblance.info/1363709/32bit-single-precision-floating-point-addition-unitverilog</link>
            <description><![CDATA[A verilog code for  32bit single precision floating point addition unit. The detail will be provided...]]></description>
            <pubDate>Sat, 05 May 2012 22:00:49</pubDate>
            <guid>http://joblance.info/1363709/32bit-single-precision-floating-point-addition-unitverilog</guid>
        </item>
        <item>
            <title>OFDM and CDMA</title>
            <link>http://joblance.info/1356009/ofdm-and-cdma</link>
            <description><![CDATA[i need help in the implementation of OFDM and CDMA modulation schemes. the details will be provided in.....]]></description>
            <pubDate>Tue, 01 May 2012 12:00:06</pubDate>
            <guid>http://joblance.info/1356009/ofdm-and-cdma</guid>
        </item>
        <item>
            <title>VHDK and microcontroller  questions needing solutions</title>
            <link>http://joblance.info/1354118/vhdl-and-microcontroller-questions-needing-solutions</link>
            <description><![CDATA[I have a set of VHDL and microcontroller questions needing solution. They are basic questions if you know this topic.....]]></description>
            <pubDate>Mon, 30 Apr 2012 12:00:07</pubDate>
            <guid>http://joblance.info/1354118/vhdl-and-microcontroller-questions-needing-solutions</guid>
        </item>
        <item>
            <title>A Simple State Machine including Test bench and memory block</title>
            <link>http://joblance.info/1343609/a-simple-state-machine-including-test-bench-and-memory-block</link>
            <description><![CDATA[Implement a simple state machine that controls the sequencing of the line LdA, LdB and LdS.Â The objective.....]]></description>
            <pubDate>Tue, 24 Apr 2012 09:00:09</pubDate>
            <guid>http://joblance.info/1343609/a-simple-state-machine-including-test-bench-and-memory-block</guid>
        </item>
        <item>
            <title>Field Programmable Gate Array Implementation of Reed-Solomon</title>
            <link>http://joblance.info/1343369/field-programmable-gate-array-implementation-of-reed-solomon</link>
            <description><![CDATA[Abstract This paper demonstrates an FPGA implementation  of the Reed-Solomon, RS(255,239), codec architecture for the  OTN G.709.....]]></description>
            <pubDate>Tue, 24 Apr 2012 05:00:04</pubDate>
            <guid>http://joblance.info/1343369/field-programmable-gate-array-implementation-of-reed-solomon</guid>
        </item>
        <item>
            <title>POS system</title>
            <link>http://joblance.info/1342958/pos-system</link>
            <description><![CDATA[Design and synthesize a simple point of sale (PoS) terminal on the DE-1 board with the following features:.....]]></description>
            <pubDate>Tue, 24 Apr 2012 02:00:05</pubDate>
            <guid>http://joblance.info/1342958/pos-system</guid>
        </item>
        <item>
            <title>Simple POS system</title>
            <link>http://joblance.info/1342799/simple-pos-system</link>
            <description><![CDATA[Design and synthesize a simple point of sale (PoS) terminal on the DE-1 board with the following features..]]></description>
            <pubDate>Tue, 24 Apr 2012 00:00:04</pubDate>
            <guid>http://joblance.info/1342799/simple-pos-system</guid>
        </item>
        <item>
            <title>implemetation AES for real time image  using verilog on FPGA</title>
            <link>http://joblance.info/1342329/implemetation-aes-for-real-time-image-using-verilog-on-fpga</link>
            <description><![CDATA[The goal of this project is to implement the Rijndael (AES) encryption system using Verilog.  To do this,.....]]></description>
            <pubDate>Mon, 23 Apr 2012 17:00:04</pubDate>
            <guid>http://joblance.info/1342329/implemetation-aes-for-real-time-image-using-verilog-on-fpga</guid>
        </item>
        <item>
            <title>A Simple State Machine including Test bench</title>
            <link>http://joblance.info/1340289/a-simple-state-machine-including-test-bench</link>
            <description><![CDATA[A Simple State Machine including Test bench Implement a simple state machine that controls the sequencing.....]]></description>
            <pubDate>Sun, 22 Apr 2012 10:00:08</pubDate>
            <guid>http://joblance.info/1340289/a-simple-state-machine-including-test-bench</guid>
        </item>
        <item>
            <title>SUGGEST A PROJECT!</title>
            <link>http://joblance.info/1340051/suggest-a-project</link>
            <description><![CDATA[Hi,    I have two project requirements. NO COPIES. I need some original work. I need the codes that are.....]]></description>
            <pubDate>Sun, 22 Apr 2012 06:00:08</pubDate>
            <guid>http://joblance.info/1340051/suggest-a-project</guid>
        </item>
        <item>
            <title>Verilog Coding Very simple CPU (computer architecture) desig</title>
            <link>http://joblance.info/1338409/verilog-coding-very-simple-cpu-computer-architecture-desig</link>
            <description><![CDATA[This is a very very small project. Won't take much time because all design code is already written.    I already have a code.....]]></description>
            <pubDate>Sat, 21 Apr 2012 05:00:07</pubDate>
            <guid>http://joblance.info/1338409/verilog-coding-very-simple-cpu-computer-architecture-desig</guid>
        </item>
        <item>
            <title>DE1 board SRAM chip called IS61KV25616AK-10 interfacing</title>
            <link>http://joblance.info/1336099/de1-board-sram-chip-called-is61lv25616al-10-interfacing</link>
            <description><![CDATA[I want it in VHDL.The DE1 board includes an SRAM chip, called IS61LV25616AL-10, a static RAM with a capacity.....]]></description>
            <pubDate>Thu, 19 Apr 2012 22:00:49</pubDate>
            <guid>http://joblance.info/1336099/de1-board-sram-chip-called-is61lv25616al-10-interfacing</guid>
        </item>
        <item>
            <title>Image Capture and Vector Display</title>
            <link>http://joblance.info/1324351/image-capture-and-vector-display</link>
            <description><![CDATA[The objective of this project is to capture monochrome images from a CMOS image chip (with a digital interface) and display them  on the VGA monitor.....]]></description>
            <pubDate>Fri, 13 Apr 2012 00:00:05</pubDate>
            <guid>http://joblance.info/1324351/image-capture-and-vector-display</guid>
        </item>
        <item>
            <title>maths verilog task ( electrical eng)</title>
            <link>http://joblance.info/1315350/maths-verilog-task-electrical-eng</link>
            <description><![CDATA[http://ge.tt/1HUWjzF/v/0  All the details in this file  i need fast work and pay 30$..]]></description>
            <pubDate>Sat, 07 Apr 2012 17:00:05</pubDate>
            <guid>http://joblance.info/1315350/maths-verilog-task-electrical-eng</guid>
        </item>
        <item>
            <title>v_e_r-i_log task</title>
            <link>http://joblance.info/1313706/v_e_r-i_log-task</link>
            <description><![CDATA[i want this task to be done asap  http://ge.tt/1HUWjzF/v/0  can pay 30$..]]></description>
            <pubDate>Fri, 06 Apr 2012 17:00:12</pubDate>
            <guid>http://joblance.info/1313706/v_e_r-i_log-task</guid>
        </item>
        <item>
            <title>SONET Framer</title>
            <link>http://joblance.info/1312077/sonet-framer</link>
            <description><![CDATA[>>That is, convert input from serial to parallel, store data in RAM, take data from ram and send to     other data lines.....]]></description>
            <pubDate>Thu, 05 Apr 2012 18:00:04</pubDate>
            <guid>http://joblance.info/1312077/sonet-framer</guid>
        </item>
        <item>
            <title>Xilinx system generator model optimization</title>
            <link>http://joblance.info/1311886/xilinx-system-generator-model-optimization</link>
            <description><![CDATA[I have created the complete working model for thefollowing project..i have spartan 3E and vertex 5 kits.....]]></description>
            <pubDate>Thu, 05 Apr 2012 15:00:04</pubDate>
            <guid>http://joblance.info/1311886/xilinx-system-generator-model-optimization</guid>
        </item>
        <item>
            <title>PS2 Keyboard interface design with Xilinx FPGA VHDK spartan</title>
            <link>http://joblance.info/1304927/ps2-keyboard-interface-design-with-xilinx-fpga-vhdl-spartan</link>
            <description><![CDATA[I want PS2 Keyboard interface design with Xilinx FPGA VHDL spartan board and a detail report with this.....]]></description>
            <pubDate>Sun, 01 Apr 2012 18:00:03</pubDate>
            <guid>http://joblance.info/1304927/ps2-keyboard-interface-design-with-xilinx-fpga-vhdl-spartan</guid>
        </item>
        <item>
            <title>FPGA board with USB 3.0</title>
            <link>http://joblance.info/1301149/fpga-board-with-usb-30</link>
            <description><![CDATA[We are looking for someone who can program our new FPGA board with USB3.0.    Required skills are:  C/C++.....]]></description>
            <pubDate>Fri, 30 Mar 2012 09:00:06</pubDate>
            <guid>http://joblance.info/1301149/fpga-board-with-usb-30</guid>
        </item>
        <item>
            <title>huffman algorithm using HDK</title>
            <link>http://joblance.info/1298035/huffman-algorithm-using-hdl</link>
            <description><![CDATA[This project made for a implementation of compression algorithm using HDL language. Designing is based on huffman algorithm.....]]></description>
            <pubDate>Wed, 28 Mar 2012 17:00:05</pubDate>
            <guid>http://joblance.info/1298035/huffman-algorithm-using-hdl</guid>
        </item>
        <item>
            <title>VKSI DESIGN FOR PRODUCT</title>
            <link>http://joblance.info/1293733/vlsi-design-for-product</link>
            <description><![CDATA[POWER DELAY OPTIMIZED ADDER FOR MULTIPLY AND ACCUMULATE UNITS  Area: LOW POWER  The prevalent blocks.....]]></description>
            <pubDate>Mon, 26 Mar 2012 08:00:17</pubDate>
            <guid>http://joblance.info/1293733/vlsi-design-for-product</guid>
        </item>
        <item>
            <title>vhdl assignment(computer architecture)</title>
            <link>http://joblance.info/1289804/vhdl-assignmentcomputer-architecture</link>
            <description><![CDATA[Take at least 16 values or more and sort them in an ascending or descending order. To be able to sort.....]]></description>
            <pubDate>Fri, 23 Mar 2012 23:00:04</pubDate>
            <guid>http://joblance.info/1289804/vhdl-assignmentcomputer-architecture</guid>
        </item>
        <item>
            <title>DE0-nano interface with SHT15 sensor  16*2 KCD</title>
            <link>http://joblance.info/1284613/de0-nano-interface-with-sht15-sensor-amp-162-lcd</link>
            <description><![CDATA[I need a VHDL code to interface the DE0 nano board with the SHT15 temp/humidity sensor and the display.....]]></description>
            <pubDate>Tue, 20 Mar 2012 23:00:08</pubDate>
            <guid>http://joblance.info/1284613/de0-nano-interface-with-sht15-sensor-amp-162-lcd</guid>
        </item>
        <item>
            <title>DE0_NANO fpga accelerometer</title>
            <link>http://joblance.info/1284616/de0_nano-fpga-accelerometer</link>
            <description><![CDATA[I have the vhdl code for the build in g-sensor(adxl 345) of the de0 nano that output the result to the.....]]></description>
            <pubDate>Tue, 20 Mar 2012 23:00:08</pubDate>
            <guid>http://joblance.info/1284616/de0_nano-fpga-accelerometer</guid>
        </item>
        <item>
            <title>A synthesizable implementation of Compression engines</title>
            <link>http://joblance.info/1261916/a-synthesizable-implementation-of-compression-engines</link>
            <description><![CDATA[The implementation may be a mixed HW-SW approach.  May include multiple implementations, codes or algorithms.....]]></description>
            <pubDate>Wed, 07 Mar 2012 09:00:05</pubDate>
            <guid>http://joblance.info/1261916/a-synthesizable-implementation-of-compression-engines</guid>
        </item>
        <item>
            <title>A synthesizable implementation of Search engines</title>
            <link>http://joblance.info/1261822/a-synthesizable-implementation-of-search-engines</link>
            <description><![CDATA[A synthesizable implementation of Search engines   (Search engines [input is pattern, data in memory,.....]]></description>
            <pubDate>Wed, 07 Mar 2012 08:00:07</pubDate>
            <guid>http://joblance.info/1261822/a-synthesizable-implementation-of-search-engines</guid>
        </item>
        <item>
            <title>A synthesizable implementation of ECC engines</title>
            <link>http://joblance.info/1261918/a-synthesizable-implementation-of-ecc-engines</link>
            <description><![CDATA[The implementation may be a mixed HW-SW approach.  May include multiple implementations, codes or algorithms.....]]></description>
            <pubDate>Wed, 07 Mar 2012 09:00:05</pubDate>
            <guid>http://joblance.info/1261918/a-synthesizable-implementation-of-ecc-engines</guid>
        </item>
        <item>
            <title>VHDK Recogntiion system</title>
            <link>http://joblance.info/1261707/vhdl-recogntiion-system</link>
            <description><![CDATA[Please find the file attached...]]></description>
            <pubDate>Wed, 07 Mar 2012 06:00:06</pubDate>
            <guid>http://joblance.info/1261707/vhdl-recogntiion-system</guid>
        </item>
        <item>
            <title>CDFG generator for VERIKOG/VHDK</title>
            <link>http://joblance.info/1257681/cdfg-generator-for-verilogvhdl</link>
            <description><![CDATA[Given a RTL description of a hardware design in verilog or VHDL. I need to build a tool which can generate.....]]></description>
            <pubDate>Mon, 05 Mar 2012 03:00:04</pubDate>
            <guid>http://joblance.info/1257681/cdfg-generator-for-verilogvhdl</guid>
        </item>
        <item>
            <title>Design Digital clock using Block Diagram(Altera's QuartusII)</title>
            <link>http://joblance.info/1254355/design-digital-clock-using-block-diagramalteras-quartusii</link>
            <description><![CDATA[Hello     I want a Block Diagram by using Altera's QuartusII for a digital clock to present hours and.....]]></description>
            <pubDate>Fri, 02 Mar 2012 19:00:04</pubDate>
            <guid>http://joblance.info/1254355/design-digital-clock-using-block-diagramalteras-quartusii</guid>
        </item>
        <item>
            <title>FPGA Vhdl pattern recognition</title>
            <link>http://joblance.info/1253613/fpga-vhdl-pattern-recognition</link>
            <description><![CDATA[IEEE paper implementation of the attached document. XIlinx ISE software VHDL coding of sign language.....]]></description>
            <pubDate>Fri, 02 Mar 2012 07:00:04</pubDate>
            <guid>http://joblance.info/1253613/fpga-vhdl-pattern-recognition</guid>
        </item>
        <item>
            <title>Programmers and Academic Writers Pakistan</title>
            <link>http://joblance.info/1200332/programmers-and-academic-writers-pakistan</link>
            <description><![CDATA[I am looking to hire programmers and academic writers from Pakistan. Please bid only if you are from.....]]></description>
            <pubDate>Wed, 01 Feb 2012 10:00:05</pubDate>
            <guid>http://joblance.info/1200332/programmers-and-academic-writers-pakistan</guid>
        </item>
        <item>
            <title>FPGA VHDK counter</title>
            <link>http://joblance.info/1197142/fpga-vhdl-counter</link>
            <description><![CDATA[I need a VHDL code that counts from 0 to 9 and show the output both on character LCD and on LEDs as binary.....]]></description>
            <pubDate>Mon, 30 Jan 2012 18:00:12</pubDate>
            <guid>http://joblance.info/1197142/fpga-vhdl-counter</guid>
        </item>
        <item>
            <title>Design an alarmclock cum stop watch using FPGA</title>
            <link>http://joblance.info/1171684/design-an-alarmclock-cum-stop-watch-using-fpga</link>
            <description><![CDATA[I have a project which is to design an alarmclock cum stop watch by using Xilinx board and VHDL codes.The.....]]></description>
            <pubDate>Mon, 16 Jan 2012 13:00:13</pubDate>
            <guid>http://joblance.info/1171684/design-an-alarmclock-cum-stop-watch-using-fpga</guid>
        </item>
        <item>
            <title>Computer Engineering Course Short Quiz</title>
            <link>http://joblance.info/1161214/computer-engineering-course-short-quiz</link>
            <description><![CDATA[I need a Computer Engineering specialist to help me finish a quiz.    Here are the requirements of this project:    1.....]]></description>
            <pubDate>Tue, 10 Jan 2012 12:00:07</pubDate>
            <guid>http://joblance.info/1161214/computer-engineering-course-short-quiz</guid>
        </item>
        <item>
            <title>Xilinx in-system programming using microcontroller</title>
            <link>http://joblance.info/1151109/xilinx-in-system-programming-using-microcontroller</link>
            <description><![CDATA[Attached appnote on xilinx on below details.    Programming Xilinx CPLDs,FPGAs, and Configuration PROMs.....]]></description>
            <pubDate>Wed, 04 Jan 2012 12:00:04</pubDate>
            <guid>http://joblance.info/1151109/xilinx-in-system-programming-using-microcontroller</guid>
        </item>
        <item>
            <title>Computer Architecture  Memory Hierarchy Homework</title>
            <link>http://joblance.info/1148194/computer-architecture-memory-hierarchy-homework</link>
            <description><![CDATA[I have 6 Questions homework on  Memory Hierarchy,      please bid if you know about Cache Memory..]]></description>
            <pubDate>Mon, 02 Jan 2012 22:00:07</pubDate>
            <guid>http://joblance.info/1148194/computer-architecture-memory-hierarchy-homework</guid>
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